 |
Dual-In-Line Tapped Delay Network "Dipline" 4 Pin Series
U
Surface Mount
Basic Specification
| Delay
Range |
1 nS to 200 nS
±5% |
| Impedance
Range |
50W to 500W
±10% |
| Number of
Sections |
1 discrete L.C.,
phase-corrected, cascadable |
| Rise-time |
Equal to delay of module
+20%, -10% |
| Distortion |
±10%
average |
| Attenuation |
0.2dB Max. |
| Working
Voltage |
50V |
| Temperature Coefficient
of Delay |
±200 p.p.m./°C
Max |
| Operating Temperature
Range |
-20°C to
+125°C |
| Encapsulation |
Flame Retardant Epoxy
Resin |
Selection Table
| Delay time,nS |
50W |
75W |
100W |
200W |
500W |
| 1 |
- |
- |
- |
065 |
- |
| 2 |
- |
- |
- |
066 |
- |
| 4 |
- |
041 |
053 |
067 |
022 |
| 5 |
027 |
015 |
054 |
068 |
001 |
| 10 |
028 |
016 |
018 |
069 |
002 |
| 20 |
029 |
017 |
055 |
070 |
003 |
| 30 |
030 |
042 |
056 |
071 |
004 |
| 40 |
031 |
043 |
057 |
072 |
005 |
| 50 |
032 |
044 |
058 |
073 |
006 |
| 60 |
- |
045 |
059 |
074 |
007 |
| 70 |
- |
046 |
060 |
075 |
008 |
| 80 |
- |
- |
061 |
076 |
009 |
| 90 |
- |
- |
062 |
077 |
010 |
| l00 |
- |
- |
063 |
078 |
011 |
| 200 |
- |
- |
- |
079 |
012 |
| ORDER CODE |
Input |
Output |
Ground |
| AU |
1 |
2 |
3 |
| BU |
1 |
3 |
2 |
| CU |
1 |
4 |
2 |
| DU |
2 |
1 |
3 |
| EU |
3 |
1 |
4 |
| FU |
4 |
1 |
3 |
Example; A Dipline 4 Pin Series,
input pin 1, output pin 2, ground pin 3, 50nS delay, 200W
Impedance, is ordered as AU073G. |
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